Conventionally, NAND-type flash memories (referred to as NAND flash memories) have been widely used as nonvolatile semiconductor memory chips. In a NAND-type flash memory, a smallest unit for recording is a page, and writing is performed in units of pages. For reading out data that have been written in response to a request from a host, it is necessary to identify, from a logical block address specified by the host, a storage location (physical block address) in which the data associated with the logical block address are actually stored in a NAND flash memory. In a memory system with semiconductor memory chips, a plurality of semiconductor memory chips each having a plurality of blocks (unit storage areas) is used so as to achieve a large capacity. In addition, a technique of using a set of blocks each included in a semiconductor memory chip to perform error correction is known.
If a plurality of blocks constitutes a set for error correction, a table (logical-to-physical translation table) that is referred to so as to see which blocks constitute a set is necessary to perform correction. There is, in this regard, a demand for reducing the size of the logical-to-physical translation table in terms of cost reduction. An object to be achieved by the embodiment is to provide a memory system in which a logical-to-physical translation table having information on sets of blocks therein can have a reduced size in performing error correction using such sets of blocks.